Unit 4: Digital Logic Families MCQ's

Updated on 2017/11/14 16:40

1.What is unique about TTL devices such as the 74SXX?
A.These devices use Schottky transistors and diodes to prevent them from going into saturation; this results in faster turn-on and turn-off times,
which translates into higher frequency operation.
B.The gate transistors are silicon (S), and the gates therefore have lower values of leakage current.
C.The S denotes the fact that a single gate is present in the IC rather than the usual package of 2–6 gates.
D.The S denotes a slow version of the device, which is a consequence of its higher power rating.

2.Which of the following logic families has the shortest propagation delay?

3.Why must CMOS devices be handled with care?
A.so they don’t get dirty
B.because they break easily
C.because they can be damaged by static electricity discharge

4.Special handling precautions should be taken when working with MOS devices. Which of the following statements is not one of these precautions?
A.All test equipment should be grounded.
B.MOS devices should have their leads shorted together for shipment and storage.
C.Never remove or insert MOS devices with the power on.
D.Workers handling MOS devices should not have grounding straps attached to their wrists.

5.What should be done to unused inputs on TTL gates?
A.They should be left disconnected so as not to produce a load on any of the other circuits and to minimize power loading on the voltage source.
B.All unused gates should be connected together and tied to V<sub<cc< sub=""> through a 1 kresistor.</sub<cc<>
C.All unused inputs should be connected to an unused output; this will ensure compatible loading on both the unused inputs and unused outputs.
D.Unused AND and NAND inputs should be tied to VCC through a 1 k resistor; unused OR and NOR inputs should be grounded.

6. Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the chip?
A.50 mW
B.82.5 mW
C.115 mW
D.165 mW

7.Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate?

8.What is the major advantage of ECL logic?
A.very high speed
B.wide range of operating voltage
C.very low cost
D.very high power

9.As a general rule, the lower the value of the speed–power product, the better the device because of its:
A.long propagation delay and high power consumption
B.long propagation delay and low power consumption

10.What is the range of invalid TTL output voltage?
A.0.0–0.4 V
B.0.4–2.4 V
C.2.4–5.0 V
D.0.0–5.0 V

11. What is the difference between the 54XX and 74XX series of TTL logic gates?
A.54XX is faster.
B.54XX is slower.
C.54XX has a wider power supply and expanded temperature range.
D.54XX has a narrower power supply and contracted temperature range.

12.An open collector output can ________ current, but it cannot ________.
A.sink, source current
B.source, sink current
C.sink, source voltage
D.source, sink voltage

13.Why is a decoupling capacitor needed for TTL ICs and where should it be connected?
A.to block dc, connect to input pins
B.to reduce noise, connect to input pins
C.to reduce the effects of noise, connect between power supply and ground
Show Answer

14.Using the schematic diagram of a TTL NAND gate, determine the state of each transistor (ON or OFF) when all inputs are high.
A.Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
B.Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
C.Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
D.Q1-OFF, Q2-ON, Q3-OFF, Q4-ON

15.If all inputs to a TTL NAND gate are low, what is the ON, OFF condition of each transistor in the circuit?
A.Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
B.Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
C.Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
D.Q1-OFF, Q2-ON, Q3-OFF, Q4-ON

16.Which of the following summarizes the important features of emitter-coupled logic (ECL)?
A.low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption
B.good noise immunity, negative logic, high-frequency capability, low power dissipation, and short propagation time
C.low propagation time, high-frequency response, low power consumption, and high output voltage swings
D.poor noise immunity, positive supply voltage operation, good low-frequency operation, and low power

17.Why is a pull-up resistor needed for an open collector gate?
A.to provide Vcc for the IC
B.to provide ground for the IC
C.to provide the HIGH voltage
D.to provide the LOW voltage

18.Why is a pull-up resistor needed when connecting TTL logic to CMOS logic?
A.to increase the output LOW voltage
B.to decrease the output LOW voltage
C.to increase the output HIGH voltage
D.to decrease the output HIGH voltage

19.The word "interfacing" as applied to digital electronics usually means:
A.a conditioning circuit connected between a standard TTL NAND gate and a standard TTL OR gate
B.a circuit connected between the driver and load to condition a signal so that it is compatible with the load
C.any gate that is a TTL operational amplifier designed to condition signals between NMOS transistors
D.any TTL circuit that is an input buffer stage

20.The rise time (tr) is the time it takes for a pulse to rise from its ________ point up to its ________ point. The fall time (tf) is the length of time it takes to fall from the ________ to the ________ point.
A.10%, 90%, 90%, 10%
B.90%, 10%, 10%, 90%
C.20%, 80%, 80%, 20%
D.10%, 70.7%, 70.7%, 10%

21.The term buffer/driver signifies the ability to provide low output currents to drive light loads.

22.PMOS and NMOS ________.
A.represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate
B.are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC
C.represent positive and negative MOS-type devices, which can be operated from differential power supplies and are compatible with operational
D.None of the above

23.Why is the operating frequency for CMOS devices critical for determining power dissipation?
A.At low frequencies, power dissipation increases.
B.thigh frequencies, the gate will only be able to deliver 70.7 % of rated power.
C.At high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power
D.At high frequencies, the gate will only be able to deliver 70.7 % of rated power and charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.

24.Ten TTL loads per TTL driver is known as:
A.noise immunity
C.power dissipation
D.propagation delay

25.The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of:
A.a CMOS inverting bilateral switch between the stages
B.a TTL tristate inverting buffer between the stages
C.a CMOS noninverting bilateral switch between the stages|
D.a CMOS buffer or inverting buffer

26. Totem-pole outputs ________ be connected ________ because ________.
A.can, in parallel, sometimes higher current is required
B.cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices
C.should, in series, certain applications may require higher output voltage
D.can, together, together they can handle larger load currents and higher output voltages

27.The high input impedance of MOSFETs:
A.allows faster switching
B.reduces input current and power dissipation
C.prevents dense packing
D.creates low-noise reactions

28.The output current capability of a single 7400 NAND gate when HIGH is called ________.
A.source current
B.sink current
D.source current of IOH

29.The time needed for an output to change from the result of an input change is known as:
A.noise immunity
C.propagation delay
D.rise time

30.The problem of interfacing IC logic families that have different supply voltages (VCC's) can be solved by using a:
B.tristate shifter
C.decoupling capacitor
D.pull-down resistor

31. What is the advantage of using low-power Schottky (LS) over standard TTL logic?
A.more power dissipation
B.less power dissipation
C.cost is less
D.cost is more

32.When is a level-shifter circuit needed in interfacing logic?
A.A level shifter is always needed.
B.A level shifter is never needed.
C.when the supply voltages are the same
D.when the supply voltages are different

33.A TTL totem-pole circuit is designed so that the output transistors:
A.are always on together
B.provide linear phase splitting
C.provide voltage regulation
D.are never on together

34.The most common TTL series ICs are:

35.Fan-out is determined by taking the ________ result(s) of ________.

36.Which family of devices has the characteristic of preventing saturation during operation?

37.How many 74LSTTL logic gates can be driven from a 74TTL gate?

38.What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?
A.The HCT series is faster.
B.The HCT series is slower.
C.The HCT series is input and output voltage compatible with TTL.
D.The HCT series is not input and output voltage compatible with TTL.

39.From the following specifications determine the fan-out for the logic family.
A.HIGH state is 16, LOW state is 8
B.HIGH state is 8, LOW state is 16
C.HIGH state is 4, LOW state is 8
D.HIGH state is 8, LOW state is 4

40.Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?
A.These are worst-case conditions.
B.These are normal conditions.
C.These are best-case conditions.
D.It doesn't matter what values are used.

41. What is the standard TTL noise margin?
A.5.0 V
B.0.0 V
C.0.8 V
D.0.4 V

42.How can ECL have both a NOR and an OR output?
A.ECL does not have this feature.
B.They are simply the inverse of each other.

43.Which logic family is characterized by a multiemitter transistor on the input?
D.None of the above

44.How is the speed–power product of a logic family determined?
A.The propagation delay in s is multiplied by the power dissipation in mW.
B.The propagation delay in ms is multiplied by the power dissipation in W.
C.The propagation delay in ns is multiplied by the power dissipation in mW.
D.The propagation delay in ns is multiplied by the power dissipation in W.

45.The problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by:
A.adding a fixed voltage-divider bias resistive network at the output of the TTL device
B.avoiding this condition and only using TTL to drive TTL
C.adding an external pull-down resistor to ground
D.adding an external pull-up resistor to VCC

46. How does the 4000 series of CMOS logic compare in terms of speed and power dissipation to the standard family of TTL logic?
A.more power dissipation and slower speed
B.more power dissipation and faster speed
C.less power dissipation and faster speed
D.less power dissipation and slower speed

Show Answer

47.What should be done with unused inputs to a TTL NAND gate?
A.let them float
B.tie them LOW
C.tie them HIGH

48.The TTL HIGH level source current is higher than the LOW level sinking current.

49. Low power dissipation is desired in large systems as it leads to
a. Lower cooling costs
b. Lower power supply and distribution costs,
c. Reduction in mechanical design problems
d. All of above

50.Which of the following logic families has the shortest propagation delay?
c. ECL d. RTL


  • Created, Edited and Notes by Prof. D. D. Khairnar, JSPM's BSCOER, Wagholi , Pune 
  • WikiNote Foundation






Created by Sujit Wagh on 2017/09/20 22:42