Unit 2: Sequential Logic Design MCQ's

Updated on 2017/11/14 16:39

1.A ripple counter's speed is limited by the propagation delay of:
A.each flip-flop
B.all flip-flops and gates
C.the flip-flops only with gates
D.only circuit gates

2.To operate correctly, starting a ring counter requires:
A.clearing all the flip-flops
B.presetting one flip-flop and clearing all the others
C.clearing one flip-flop and presetting all the others
D.presetting all the flip-flops

3.What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?
A.PIPO
B.SISO
C.SIPO
D.PISO

4.Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
A.input clock pulses are applied only to the first and last stages
B.input clock pulses are applied only to the last stage
C.input clock pulses are not used to activate any of the counter stages
D.input clock pulses are applied simultaneously to each stage

5.One of the major drawbacks to the use of asynchronous counters is that:
A.low-frequency applications are limited because of internal propagation delays
B.high-frequency applications are limited because of internal propagation delays
C.Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.
D.Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.

6. Which type of device may be used to interface a parallel data format with external equipment's serial format?
A.key matrix
B.UART
C.memory chip
D.serial-in, parallel-out

7.When the output of a tri-state shift register is disabled, the output level is placed in a:
A.float state
B.LOW state
C.high impedance state
D.float state and a high impedance state

8.A comparison between ring and johnson counters indicates that:
A.a ring counter has fewer flip-flops but requires more decoding circuitry
B.a ring counter has an inverted feedback path
C.a johnson counter has more flip-flops but less decoding circuitry
D.a johnson counter has an inverted feedback path

9.A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
A.shift register sequencer
B.clock
C.johnson
D.binary

10.What is meant by parallel-loading the register?
A.Shifting the data in all flip-flops simultaneously
B.Loading data in two of the flip-flops
C.Loading data in all four flip-flops at the same time
D.Momentarily disabling the synchronous SET and RESET inputs

11.What is a shift register that will accept a parallel input and can shift data left or right called?
A.tri-state
B.end around
C.bidirectional universal
D.conversion

12.What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
A.The output word decreases by 1.
B.The output word decreases by 2.
C.The output word increases by 1.
D.The output word increases by 2.

13.Mod-6 and mod-12 counters are most commonly used in:
A.frequency counters
B.multiplexed displays
C.digital clocks
D.power consumption meters

14.Propagation delay time, tPLH, is measured from the ________.
A.triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
B.triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
C.preset input to the LOW-to-HIGH transition of the output
D.clear input to the HIGH-to-LOW transition of the output

15.How is a J-K flip-flop made to toggle?
A.J = 0, K = 0
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 1, K = 1

16.How many flip-flops are in the 7475 IC?
A.1
B.2
C.4
D.8

17.How many flip-flops are required to produce a divide-by-128 device?
A.1
B.4
C.6
D.7

18.Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
A.True
B.False

19. Which of the following is correct for a D latch?
A.The output toggles if one of the inputs is held HIGH.
B.Q output follows the input D when the enable is HIGH.
C.Only one of the inputs can be HIGH at a time.
D.The output complement follows the input when enabled.

20.A J-K flip-flop is in a "no change" condition when ________.
A.J = 1, K = 1
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 0, K = 0

21.A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
A.clock is LOW
B.slave is transferring
C.flip-flop is reset
D.clock is HIGH

22. What does the triangle on the clock input of a J-K flip-flop mean?
A.level enabled
B.edge-triggered

23.On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
A.the clock pulse is LOW
B.the clock pulse is HIGH
C.the clock pulse transitions from LOW to HIGH
D.the clock pulse transitions from HIGH to LOW

24. A positive edge-triggered D flip-flop will store a 1 when ________.
A.the D input is HIGH and the clock transitions from HIGH to LOW
B.the D input is HIGH and the clock transitions from LOW to HIGH
C.the D input is HIGH and the clock is LOW
D.the D input is HIGH and the clock is HIGH

25.If an input is activated by a signal transition, it is ________.
A.edge-triggered
B.toggle triggered
C.clock triggered
D.noise triggered
Show Answer

26. Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
A.True
B.False

27. How many flip-flops are required to make a MOD-32 binary counter?
A.3
B.45
C.5
D.6

28.Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?
A.50,000
B.65,536
C.25,536
D.15,536

29.A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?
A.10002
B.10102
C.10112
D.11012

30.The terminal count of a modulus-11 binary counter is ________.
A.1010
B.1000
C.1001
D.1100

31.List which pins need to be connected together on a 7493 to make a MOD-12 counter.
A.12 to 1, 11 to 3, 9 to 2
B.12 to 1, 11 to 3, 12 to 2
C.12 to 1, 11 to 3, 8 to 2
D.12 to 1, 11 to 3, 1 to 2

32.How can a digital one-shot be implemented using HDL?
A.By using a resistor and a capacitor
B.By applying the concept of a counter
C.By using a library function
D.By applying a level trigger

33. Three cascaded decade counters will divide the input frequency by ________.
A.10
B.20
C.100
D.1,000

34. Which of the following statements are true?
[A].Asynchronous events do not occur at the same time.
[B].Asynchronous events are controlled by a clock.
[C].Synchronous events do not need a clock to control them.
[D].Only asynchronous events need a control clock.

35. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?
A.tristate
B.end around
C.universal
D.conversion

36. By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register.
A.parallel-in, serial, parallel
B.serial-in, parallel, serial
C.series-parallel-in, series, parallel
D.bidirectional in, parallel, series

37. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?
A.parallel-in, parallel-out
B.parallel-in, serial-out
C.serial-in, parallel-out
D.serial-in, serial-out

38. What is the function of a buffer circuit?
A.to provide an output that is inverted from that on the input
B.to provide an output that is equal to its input
C.to clean up the input
D.to clean up the output

39. What is the preset condition for a ring shift counter?
A.all FFs set to 1
B.all FFs cleared to 0
C.a single 0, the rest 1
D.a single 1, the rest 0

40.Which is not characteristic of a shift register?
A.Serial in/parallel in
B.Serial in/parallel out
C.Parallel in/serial out
D.Parallel in/parallel out

41.To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________.
A.divide-by-4 clock pulse
B.sequence generator
C.strobe line
D.multiplexer

42.Another way to connect devices to a shared data bus is to use a ________.
A.circulating gate
B.transceiver
C.bidirectional encoder
D.strobed latch

43.To serially shift a nibble (four bits) of data into a shift register, there must be ________.
A.one clock pulse
B.four clock pulses
C.eight clock pulses
D.one clock pulse for each 1 in the data

44.Computers operate on data internally in a ________ format.
A.tristate
B.universal
C.parallel
D.serial

45.In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?
A.1
B.2
C.4
D.8

46.How much storage capacity does each stage in a shift register represent?
A.One bit
B.Two bits
C.Four bits (one nibble)
D.Eight bits (one byte)

47.When the output of a tristate shift register is disabled, the output level is placed in a:
A.float state
B.LOW state
C.high-impedance state
D.float or high-impedance state

48. MOD-6 and MOD-12 counters and multiples are most commonly used as:
A.frequency counters
B.multiplexed displays
C.digital clocks
D.power consumption meters

49.Which of the following is an invalid state in an 8421 BCD counter?
A.0011
B.1001
C.1000
D.1100

50.How many different states does a 2-bit asynchronous counter have?
A.1
B.2
C.4
D.8

References

  • Created, Edited and Notes by Prof. D. D. Khairnar, JSPM's BSCOER, Wagholi , Pune 
  • WikiNote Foundation

 

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Created by Sujit Wagh on 2017/09/20 22:41