Unit 1: Combinational Logic Design MCQ's

Updated on 2017/11/14 16:37

1.How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
A. 1
B .2
C. 4
D. 8

2.Which of the figures shown below represents the exclusive-NOR gate?

2.png
A. a
B  b
C. c
D. d

 

3.Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

3.png

A. a
B. b
C. c
D. d

4.For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. What is the status of the Y output?
4.png

A.LOW
B.HIGH
C.Don't Care
D.Cannot be determined

5.For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH. What is the status of the Y output?

5.png
A.LOW
B.HIGH
C.Don't Care
D.Cannot be determined

6.Convert BCD 0001 0010 0110 to binary.
A.1111110
B.1111101
C.1111000
D.1111111

7.A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH?
1506159062629-681.png

A.
B.
C.
D.

8.Convert BCD 0001 0111 to binary.
A.10101
B.10010
C.10001
D.11000

9.Which of the figures in figure (a to d) is equivalent to figure (e)?

A. a
B .b
C. c
D. d

10.How many data select lines are required for selecting eight inputs?
A. 1
B. 2
C. 3
D. 4

11.The simplest equation which implements the K-map shown below is:
1506159178788-497.png
A.1506159259741-895.png
B.1506159282889-293.png
C.1506159299915-759.png
D.1506159313479-349.png

12.How many 1-of-16 decoders are required for decoding a 7-bit binary number?
A. 5
B. 6
C. 7
D. 8

13.Which of the following logic expressions represents the logic diagram shown?
1506159355558-944.png
A.1506159451817-137.png
B.1506159467851-599.png
C.1506159479352-126.png
D.1506159494323-511.png

14.The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.)
A. AND/OR
B. NAND
C. NOR
D. OR/AND
Show Answer

15.Which of the following statements accurately represents the two BEST methods of logic circuit simplification?
A. Boolean algebra and Karnaugh mapping
B. Karnaugh mapping and circuit waveform analysis
C. Actual circuit trial and error evaluation and waveform analysis
D. Boolean algebra and actual circuit trial and error evaluation

16. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs?
1506159792246-987.png
A. All are HIGH.
B. All are LOW.
C. All but are LOW.
D. All but are HIGH.

17.Which of the following combinations cannot be combined into K-map groups?
A. Corners in the same row
B. Corners in the same column
C .Diagonal corners
D. Overlapping combinations

18.As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the possible faults listed, select the one that most probably is causing the problem.
A. A defective IC chip that is drawing excessive current from the power supply
B. A solar bridge between the inputs on the first IC chip on the board
C. An open input on the first IC chip on the board
D. A defective output IC chip that has an internal open to Vcc

19.Which gate is best used as a basic comparator?
A. NOR
B. OR
C. Exclusive-OR
D. AND

20.The device shown here is most likely a ________.
1506159823836-959.png
A. comparator
B. multiplexer
C. demultiplexer
D. parity generator

21. In VHDL, macrofunctions is/are:
A. digital circuits.
B. analog circuits.
C. a set of bit vectors.
D. preprogrammed TTL devices.

22.Which of the following expressions is in the product-of-sums form?
A. (A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD

23.Which of the following is an important feature of the sum-of-products form of expressions?
A. All logic circuits are reduced to nothing more than simple AND and OR operations.
B. The delay times are greatly reduced over other forms.
C. No signal must pass through more than two gates, not including inverters.
D. The maximum number of gates that any signal must pass through is reduced by a factor of two.

24.For the device shown here, assume the D input is LOW, both S inputs are LOW, and the input is LOW. What is the status of the outputs?
1506159873402-788.png
A. All are HIGH.
B. All are LOW.
C. All but are LOW.
D.All but are HIGH.

25.An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help isolate the problem?
A. Current tracer
B. Logic probe
C. Oscilloscope
D. Logic analyzer

26. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
A. A > B = 1, A < B = 0, A < B = 1
B. A > B = 0, A < B = 1, A = B = 0
C. A > B = 1, A < B = 0, A = B = 0
D. A > B = 0, A < B = 1, A = B = 1

27.A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?
A. The output of the gate appears to be open.
B. The dim indication on the logic probe indicates that the supply voltage is probably low.
C. The dim indication is a result of a bad ground connection on the logic probe.
D. The gate may be a tristate device.

28.Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What are the values for the sum and carry output?
A. 4321 = 0111, Cout = 0
B. 4321 = 1111, Cout = 1
C. 4321 = 1011, Cout = 1
D. 4321 = 1100, Cout = 1

29.Each "1" entry in a K-map square represents:
A. a HIGH for each input truth table condition that produces a HIGH output.
B. a HIGH output on the truth table for all LOW input combinations.
C. a LOW output for all possible HIGH input conditions.
D. a DON'T CARE condition for all possible input truth table combinations.

30.Looping on a K-map always results in the elimination of:
A. variables within the loop that appear only in their complemented form.
B. variables that remain unchanged within the loop.
C. variables within the loop that appear in both complemented and uncomplemented form.
D. variables within the loop that appear only in their uncomplemented form.

31. What will a design engineer do after he/she is satisfied that the design will work?
A. Put it in a flow chart
B. Program a chip and test it
C. Give the design to a technician to verify the design
D. Perform a vector test

32.Based on the indications of probe A in the figure given below, what is wrong, if anything, with the circuit?
1506159906652-779.png
A. The logic probe is unable to determine the state of the circuit at that point and is blinking to alert the technician to the problem.
B. The output appears to be shorted to Vcc, but is being pulsed by the pulser.
C.The output appears to be LOW, but is being pulsed by the pulser.
D.Nothing appears to be wrong at that point.

33.What is the indication of a short on the input of a load gate?
A. Only the output of the defective gate is affected.
B. There is a signal loss to all gates on the node.
C. The affected node will be stuck in the LOW state.
D. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.

34.In HDL, LITERALS is/are:
A. digital systems.
B. scalars.
C. binary coded decimals.
D. a numbering system.

35.Which of the following expressions is in the sum-of-products form?
A. (A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD

.36.The carry propagation can be expressed as ________.
A. Cp = AB
B. Cp = A + B

37.Which of the K-maps given below represents the expression X = AC + BC + B?
1506159952544-638.png
A. a
B. b
C. c
D. d

38.A decoder can be used as a demultiplexer by ________.
A. tying all enable pins LOW
B. tying all data-select lines LOW
C. tying all data-select lines HIGH
D. using the input lines for data selection and an enable line for data input

39.How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010?
A. 1
B. 2
C. 3
D. 4

40.Which statement below best describes a Karnaugh map?A.
A. Karnaugh map can be used to replace Boolean rules.
B.The Karnaugh map eliminates the need for using NAND and NOR gates.
C.Variable complements can be eliminated by using Karnaugh maps.
D.Karnaugh maps provide a visual approach to simplifying Boolean expressions.

41.For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?
1506160065349-380.png
A. a
B. b
C. c
D. d

42.A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001?
A .0
B. 3
C. 9
D.None. All outputs are HIGH.

43.Solve the network in the figure given below for X.
1506160116426-820.png
A. A + BC + D
B. ((A + B)C) + D
C. D(A + B + C)
D. (AC + BC)D

44.A full-adder has a Cin = 0. What are the sum () and the carry (Cout) when A = 1 and B = 1?
A.= 0, Cout = 0
B.= 0, Cout = 1
C.= 1, Cout = 0
D.= 1, Cout = 1

45.What type of logic circuit is represented by the figure shown below?
1506160148171-644.png
A.XOR
B.XNOR
C.XAND
D.XNAND

46.The device shown here is most likely a ________.
1506160171088-329.png
A.comparator
B.multiplexer
C.demultiplexer
D.parity generator

47.The design concept of using building blocks of circuits in a PLD program is called a(n):
A.hierarchical design.
B.architectural design.
C.digital design.
D.verilog.

48.When adding an even parity bit to the code 110010, the result is ________.
A.1110010
B.1111001
C.110010
D.001101

49.Which of the following combinations of logic gates can decode binary 1101?
A.One 4-input AND gate
B.One 4-input AND gate, one OR gate
C.One 4-input NAND gate, one inverter
D.One 4-input AND gate, one inverter

50.What is the indication of a short to ground in the output of a driving gate?
A.Only the output of the defective gate is affected.
B.There is a signal loss to all load gates.
C.The node may be stuck in either the HIGH or the LOW state.
D.The affected node will be stuck in the HIGH state.

References

  • Created, Edited and Notes by Prof. D. D. Khairnar, JSPM's BSCOER, Wagholi , Pune 
  • WikiNote Foundation
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Created by Sujit Wagh on 2017/09/20 22:40