ROM as PLD, Programmable Logic Array (PLA), Programmable Array Logic (PAL)

Updated on 2017/11/17 11:39

Syllabus

  • ROM as PLD, Programmable Logic Array (PLA), Programmable Array Logic (PAL)

Introduction to PLDs

PLDs.png

  • ROM: Programmable OR array
  • PLA:
    • Programmable Logic Array
    • Programmable OR – AND Arrays
  • PAL:
    • Programmable Array Logic
    • Programmable AND array, fixed OR
  • GAL:
    • Generic Array Logic
    • Can be configured to emulate many earlier PLDs including those with internal Flip-Flops
  • CPLD: Complex PLD
  • FPGA: Field Programmable Gate Array

PROM

The first PLD is PROM was introduced in 1970. PROMs was introduced for use as computer memories in which to store program instructions and constant data values. PROM have fixed AND plane and programmable OR plane. PROM can be use to program any combinational logics with limited numbers of inputs and outputs. Given n variables, it would necessary to have 2n AND gates, one for each possible minterm. A figure below shows the unprogrammed PROM for 3 inputs and 3 outputs, where AND plane is fixed and OR plane is programmable. The programmable links in OR array can be implemented as fused link, or as EPROM transistor or E2PROM cells depend on vendors. PROMs are useful for equations requiring a large number of product terms, but they can support few inputs as every input combination is always decoded and used.

Two basic versions of PROM:
1) Mask-Programmable: can be programmed only by the manufacturer. Mask-programmable chip has less delay because connections within the device can be hardwired during manufacture.
2) Field-Programmable: can be programmed by the end-user .Field-programmable chips are less expensive, and can be programmed immediately. The Field Programmable PROM developed into two types, the Erasable Programmable Read-Only Memory (EPROM) and the Electrically Erasable Programmable Read-Only Memory (E2PROM). The E2PROM has the advantage of being erasable and reprogrammable many times.

Implementation procedure

  1. Preparation in SOP (sum of products) form.
  2. Obtain the minimum SOP form to reduce the number of product terms to a minimum.
  3. Decide the input connection of the AND matrix for generating the required product term.
  4. Then decide the input connections of OR matrix to generate the sum terms.
  5. Decide the connections of invert matrix.
  6. Program the PLA.

Advantages over read-only memory

The desired outputs for each combination of inputs could be programmed into a read-only memory, with the inputs being loaded onto the address bus and the outputs being read out as data. However, that would require a separate memory location for every possible combination of inputs, including combinations that are never supposed to occur, and also duplicating data for "don't care" conditions (for example, logic like "if input A is 1, then, as far as output X is concerned, we don't care what input B is": in a ROM this would have to be written out twice, once for each possible value of B, and as more "don't care" inputs are added, the duplication grows exponentially); therefore, a programmable logic array can often implement a piece of logic using fewer transistors than the equivalent in read-only memory. This is particularly valuable when it is part of a processing chip where transistors are scarce (for example, the original 6502 chip contained a PLA to direct various operations of the processor).

Applications

  1. One application of a PLA is to implement the control over a datapath. It defines various states in an instruction set, and produces the next state (by conditional branching). [e.g. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and will define the actions of the control in state 4]. Programmable logic arrays should correspond to a state diagram for the system.

Other commonly used programmable logic devices are PAL, CPLD and FPGA.

  1. Note that the use of the word "programmable" does not indicate that all PLAs are field-programmable; in fact many are mask-programmed during manufacture in the same manner as a mask ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPGA (Field-programmable gate array), or less frequently FPLA (Field-programmable logic array)..

PLA vs ROM

ROM (Read Only Memory) and PLA (Programmable Logic Array) are used to implement logic functions. Both of them use the ‘Sum of Products’ logic configuration, which consists of a primary array of AND gates and a secondary array of OR gates. The OR function (Sum) is applied to outputs of AND (product) arrays.

What is the difference between ROM and PLA?

  1. In PLA both AND and OR arrays are configurable unlike in ROM, whereas only the OR gates array is configurable.
  2. PLA has the capability to take ‘don’t care terms’ (Boolean overlaps) into account in which ROMs are incapable.
  3. ROM has all the combinations of product terms, and therefore, considered as the most general purpose combinational logic device in contrast to PLA, which doesn’t have all the combinations.

ROM (Read Only Memory)

ROM is made of an AND gates array and OR gates array. AND array provides all the combinations of inputs, and OR array is used to select the necessary combinations. Therefore, AND array is always fixed. For example, in a three input (let say) system, AND array produces all the combinations (product terms) of ABC, ABC’, AB’C, AB’C’, A’BC, A’BC’, A’B’C, A’B’C’ where ’ implies the complement (NOT).

Then an OR gate can be used to select the necessary product terms to implement the given logic function. Any logic function of A, B, C can be implemented using those product terms.

For example

f(A,B,C) = AB + BC = ABC + ABC’ + A’BC

Likewise an array of OR gates can implement an array of logic functions. Therefore ROM is used to store programs. Programming the ROM means configuring those OR array by selecting the necessary products.

PLA (Programmable Logic Array)

PLA too is made of two OR and AND arrays, but both the arrays are configurable unlike in ROM. This also provides a ‘Sum of Products’ term, but in a different way. Since terms for AND gates are also possible, it can give more product terms like AB, BC’, C etc. Therefore it is much easier to implement logic functions compared to ROM.

For example, AB + BC can be directly implemented by selecting A, B for one AND gate, B,C for another AND gate and making outputs of those AND gates to inputs of an OR gate.

PLA-Structure-Schematic

 

PLD (Programmable Logic Devices)

PLD are chips which contained programmable circuit. These chips contained large digital gates that could be programmed. This offered designers the flexibility to program the chip according to the circuit design requirements.

PLA(Programmable Logic Array)

PLA(Programmable Logic Array) and PAL(Programmable Array Logic) are Programmable Logic Devices which had planes of AND and OR gates interconnected to each other and which could be programmed.

First PLA were discovered. The block diagram of the structure of PLA inside a chip is shown below.

PLA-structure-inside-chip.png

As shown above, the PLA consisted of planes of input buffers and inverters, plane of AND gates and plane of OR gates. This structure was developed utilizing the fact that any logic function can be expressed as sum of product of minterms. Each of the connection between the planes could be connected or left disconnected and thus implement the desired logic function. Thus this gave a flexibility of realizing digital logic circuit.

A closer look at the internal structure of the connection between the plane is shown below.

PLA-plane-connections.png

In technical writing and design the following schematic drawing is commonly used.

PAL(Programmable Array Logic)

A PAL is also a PLD(programmable Logic Device) but in case of PAL as opposed to PLA, the OR gate plane is fixed while the AND plane is programmable. This has improved performance and improved fabrication margin. That is, because a PLA have both programmable AND and OR planes there was higher potential that the PLD was corrupted.

An example of PAL circuit is shown below.

PAL-AND-circuit.png

Difference between PLA and PAL.

  • PLA has both programmable AND and OR planes whereas PAL has only programmable AND planes and OR plane is fixed
  • PLA has more flexibility in the logic circuit function implementation than PAL
  • PAL is simpler to manufacture than PLA
  • PLA have reduced speed performance
  • PAL devices are manufactured in smaller size.

PAL-Design

Fig: PAL Design

References

  • Created and developed by Prof. Hrishikesh Dhanwate, ICOER, Pune
  • WikiNote Foundation
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Created by Sujit Wagh on 2017/11/13 15:21