Unit 3: Algorithmic State Machines

Updated on 2017/08/18 11:49

Table of Contents

Syllabus and Notes

  • Algorithmic State Machines: Finite State Machines (FSM) and ASM, ASM charts, notations, construction of ASM chart and realization for sequential circuits, Sequence Generator, Types of Counters.
  • VHDL: Introduction to HDL, Data Objects & Data Types, Attributes., VHDL- Library, Design Entity, Architecture, Modeling Styles, Concurrent and Sequential Statements
  • Design Examples: VHDL for Combinational Circuits-Adder, MUX, VHDL for Sequential Circuits, Synchronous and Asynchronous Counter.

References

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Created by Dark Knight on 2017/08/18 11:49